A variety of conventional flash memory devices are described in the following US Patents and patent documents: U.S. Pat. Nos. 6,751,766; 7,196,946; 7,203,874; US 2006/0101193 A1; US 2007/0180346 A1.
The state of the art is believed to be described by the following publications inter alia:
[1] “Interleaving policies for flash memory”, U.S. Pat. No. 20070168625
[2] “Minimization of FG-FG coupling in flash memory”, U.S. Pat. No. 6,996,004
[3] “Compensating for coupling during read operations on non-volatile memory”, U.S. Pat. No. 2006221692
[4] Construction of Rate (nμ1)/n Punctured Convolution Code with Minimum Required SNR Criterion, Pil J. Lee, IEEE Trans. On Comm. Vol. 36, NO. 10, October 1988
[5] “Introduction to Coding Theory”, Ron M. Roth, Cambridge University Press, 2006, particularly chapters 5 and 8 re BCH.
[6] “Sensing margin analysis of MLC flash memories using a novel unified statistical model”, Young-Gu Kim, Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on . . . .
[7] “Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods”, Quentin Rafhay, Solid-State Electronics Volume 51, Issue 4, April 2007, Pages 585-592.
[8] “Statistical simulations for flash memory reliability analysis and prediction”, Larcher, L, Electron Devices, IEEE Transactions on, Volume 51, Issue 10, October 2004 Page(s): 1636-1643.
Conventional flash memory technology is described in the following textbooks inter alia:
[9] Paulo Cappelletti, Clara Golla, Piero Olivo, Enrico Zanoni, “Flash Memories”, Kluwer Academic Publishers, 1999
[10] G. Campardo, R. Micheloni, D. Novosel, “CLSI-Design of Non-Volatile Memories”, Springer Berlin Heidelberg N.Y., 2005.
[11] Introduction to Probability, Charles M. Grinstead, Swarthmore College, J. Laurie Snell, Dartmouth College
The disclosures of all publications and patent documents mentioned in the specification, and of the publications and patent documents cited therein directly or indirectly, are hereby incorporated by reference. U.S. Pat. No. 6,996,004 entitled “Minimization of FG-FG coupling in flash memory” describes that “multiple passes of the loop of program verify and programming steps are performed for minimizing the effects of FG-FG coupling during programming a flash memory device . . . [F]or programming a group of at least one flash memory cell of an array, a first pass of program verify and programming steps is performed until each flash memory cell of the group attains a threshold voltage that is at least X % of a program verify level but less than the program verify level. Then, a second pass of program verify and programming steps are performed until each flash memory cell of the group attains substantially the program verify level for the threshold voltage.”
The disclosures of all publications and patent documents mentioned in the specification, and of the publications and patent documents cited therein directly or indirectly, are hereby incorporated by reference.